Patents

1.  Electronic Devices and Systems, and Methods for Making and Using the Same

  • Publication number: 20170117366
  • Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
  • Type: Application
  • Filed: January 4, 2017
  • Publication date: April 27, 2017
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

2.  Advanced Transistors with Punch Through Suppression

  • Publication number: 20170040419
  • Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
  • Type: Application
  • Filed: October 20, 2016
  • Publication date: February 9, 2017
  • Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson

3.  Buried Channel Deeply Depleted Channel Transistor

  • Publication number: 20170025457
  • Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
  • Type: Application
  • Filed: October 4, 2016
  • Publication date: January 26, 2017
  • Inventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson

4.  Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof

  • Publication number: 20170012044
  • Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an anaolog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
  • Type: Application
  • Filed: September 21, 2016
  • Publication date: January 12, 2017
  • Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang

5.  Electronic Devices and Systems, and Methods for Making and Using the Same

  • Publication number: 20160358918
  • Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
  • Type: Application
  • Filed: August 19, 2016
  • Publication date: December 8, 2016
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

6.  Advanced transistors with punch through suppression

  • Patent number: 9508800
  • Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
  • Type: Grant
  • Filed: December 22, 2015
  • Date of Patent: November 29, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson

7.  CMOS gate stack structures and processes

  • Patent number: 9508728
  • Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
  • Type: Grant
  • Filed: January 21, 2016
  • Date of Patent: November 29, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Thomas Hoffmann, Pushkar Ranade, Scott E. Thompson

8.  Transistor with Threshold Voltage Set Notch and Method of Fabrication Thereof

  • Publication number: 20160336318
  • Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD, so that the body bias can be tuned separately from VT for a given device.
  • Type: Application
  • Filed: June 24, 2016
  • Publication date: November 17, 2016
  • Inventors: Reza Arghavani, Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve

9.  Low power semiconductor transistor structure and method of fabrication thereof

  • Patent number: 9496261
  • Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
  • Type: Grant
  • Filed: August 19, 2013
  • Date of Patent: November 15, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachrin R. Sonkusale, Weimin Zhang

10.  Buried channel deeply depleted channel transistor

  • Patent number: 9478571
  • Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.
  • Type: Grant
  • Filed: May 23, 2014
  • Date of Patent: October 25, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Teymur Bakhishev, Lingquan Wang, Dalong Zhao, Pushkar Ranade, Scott E. Thompson

11.  CMOS Structures and Processes Based on Selective Thinning

  • Publication number: 20160307907
  • Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.
  • Type: Application
  • Filed: June 3, 2016
  • Publication date: October 20, 2016
  • Inventors: Scott E. Thompson, Thomas Hoffmann, Lance Scudder, Urupattur C. Sridharan, Dalong Zhao, Pushkar Ranade, Michael Duane, Paul Gregory

12.  Transistor with threshold voltage set notch and method of fabrication thereof

  • Patent number: 9418987
  • Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD, so that the body bias can be tuned separately from VT for a given device.
  • Type: Grant
  • Filed: June 5, 2014
  • Date of Patent: August 16, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Reza Arghavani, Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve

13.  Integrated Circuit Devices and Methods

  • Publication number: 20160232964
  • Abstract: An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.
  • Type: Application
  • Filed: April 21, 2016
  • Publication date: August 11, 2016
  • Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Robert Rogenmoser, Damodar R. Thummalapally

14.  Method for fabricating multiple transistor devices on a substrate with varying threshold voltages

  • Patent number: 9406567
  • Abstract: Fabrication of a first device on a substrate is performed by exposing a first device region, removing a portion of the substrate to create a trench in the first device region, forming a screen layer with a first dopant concentration in the trench on the substrate, and forming an epitaxial channel on the screen layer having a first thickness. On or more other devices are similarly formed on the substrate independent of each other with epitaxial channels of different thicknesses than the first thickness. Devices with screen layers having the same dopant concentration but with different epitaxial channel thicknesses have different threshold voltages. Thus, a wide variety of threshold voltage devices can be formed on the same substrate. Further threshold voltage setting can be achieved through variations in the dopant concentration of the screen layers.
  • Type: Grant
  • Filed: February 28, 2012
  • Date of Patent: August 2, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Lucian Shifren, Pushkar Ranade, Thomas Hoffmann, Scott E. Thompson

15.  Epitaxial Channel Transistors and Die With Diffusion Doped Channels

  • Publication number: 20160211346
  • Abstract: Semiconductor structures can be fabricated by implanting a screen layer into a substrate, with the screen layer formed at least in part from a low diffusion dopant species. An epitaxial channel of silicon or silicon germanium is formed above the screen layer, and the same or different dopant species is diffused from the screen layer into the epitaxial channel layer to form a slightly depleted channel (SDC) transistor. Such transistors have inferior threshold voltage matching characteristics compared to deeply depleted channel (DDC) transistors, but can be more easily matched to legacy doped channel transistors in system on a chip (SoC) or multiple transistor semiconductor die.
  • Type: Application
  • Filed: March 28, 2016
  • Publication date: July 21, 2016
  • Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson

16.  CMOS structures and processes based on selective thinning

  • Patent number: 9391076
  • Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.
  • Type: Grant
  • Filed: December 18, 2014
  • Date of Patent: July 12, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Scott E. Thompson, Thomas Hoffmann, Lance Scudder, Urupattur C. Sridharan, Dalong Zhao, Pushkar Ranade, Michael Duane, Paul Gregory

17.  Advanced Transistors with Punch Through Suppression

  • Publication number: 20160181370
  • Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
  • Type: Application
  • Filed: December 22, 2015
  • Publication date: June 23, 2016
  • Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson

18.  Method for fabricating a transistor with reduced junction leakage current

  • Patent number: 9368624
  • Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
  • Type: Grant
  • Filed: July 24, 2015
  • Date of Patent: June 14, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane

19.  Integrated circuit devices and methods

  • Patent number: 9362291
  • Abstract: An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.
  • Type: Grant
  • Filed: August 9, 2014
  • Date of Patent: June 7, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Robert Rogenmoser, Damodar R. Thummalapally

20.  CMOS Gate Stack Structures and Processes

  • Publication number: 20160141292
  • Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
  • Type: Application
  • Filed: January 21, 2016
  • Publication date: May 19, 2016
  • Inventors: Thomas Hoffmann, Pushkar Ranade, Scott E. Thompson

21.  CMOS gate stack structures and processes

  • Patent number: 9281248
  • Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
  • Type: Grant
  • Filed: April 30, 2014
  • Date of Patent: March 8, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Thomas Hoffmann, Pushkar Ranade, Scott E. Thompson

22.  Advanced transistors with punch through suppression

  • Patent number: 9263523
  • Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
  • Type: Grant
  • Filed: February 24, 2014
  • Date of Patent: February 16, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson

23.  Digital Circuits Having Improved Transistors, and Methods Therefor

  • Publication number: 20160020768
  • Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
  • Type: Application
  • Filed: September 28, 2015
  • Publication date: January 21, 2016
  • Inventors: Scott E. Thompson, Lawrence T. Clark

24.  Analog circuits having improved transistors, and methods therefor

  • Patent number: 9231541
  • Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
  • Type: Grant
  • Filed: September 29, 2014
  • Date of Patent: January 5, 2016
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Lawerence T. Clark, Scott E. Thompson

25.  High uniformity screen and epitaxial layers for CMOS devices

  • Patent number: 9196727
  • Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
  • Type: Grant
  • Filed: November 6, 2014
  • Date of Patent: November 24, 2015
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane

26.  High Uniformity Screen and Epitaxial Layers for CMOS Devices

  • Publication number: 20150333144
  • Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
  • Type: Application
  • Filed: July 24, 2015
  • Publication date: November 19, 2015
  • Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane

27.  Digital circuits having improved transistors, and methods therefor

  • Patent number: 9184750
  • Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
  • Type: Grant
  • Filed: May 10, 2013
  • Date of Patent: November 10, 2015
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Scott E. Thompson, Lawrence T. Clark

28.  ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING SAME

  • Publication number: 20150255350
  • Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sigma VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
  • Type: Application
  • Filed: March 9, 2015
  • Publication date: September 10, 2015
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

29.  Porting a circuit design from a first semiconductor process to a second semiconductor process

  • Patent number: 9117746
  • Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated.
  • Type: Grant
  • Filed: July 21, 2014
  • Date of Patent: August 25, 2015
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Samuel Leshner

30.  Analog transistor

  • Patent number: 9093469
  • Abstract: An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants. The channel is supported on a screen layer doped to have an average dopant density at least five times as great as the average dopant density of the substantially undoped channel which, in turn, is supported by a doped well having an average dopant density at least twice the average dopant density of the substantially undoped channel.
  • Type: Grant
  • Filed: May 9, 2014
  • Date of Patent: July 28, 2015
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Lucian Shifren, Scott E. Thompson, Paul E. Gregory

31.  Semiconductor devices having fin structures and fabrication methods thereof

  • Patent number: 9054219
  • Abstract: A method of fabricating semiconductor devices includes providing a semiconducting substrate. The method also includes defining a heavily doped region at a surface of the semiconducting substrate in at least one area of the semiconducting substrate, where the heavily doped region includes a heavily doped layer having a doping concentration greater than a doping concentration of the semiconducting substrate. The method also includes forming an additional layer of semiconductor material on the semiconducting substrate, the additional layer comprising a substantially undoped layer. The method further includes applying a first removal process to the semiconducting substrate to define an unetched portion and an etched portion, where the unetched portion defines a fin structure, and the etched portion extends through the additional layer, and then isolating the fin structure from other structures.
  • Type: Grant
  • Filed: February 5, 2014
  • Date of Patent: June 9, 2015
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Thomas Hoffmann, Scott E. Thompson

32.  Deeply depleted MOS transistors having a screening layer and methods thereof

  • Patent number: 9041126
  • Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.
  • Type: Grant
  • Filed: September 5, 2013
  • Date of Patent: May 26, 2015
  • Assignee: Mie Fujitsu Semiconductor Limited
  • Inventors: Thomas Hoffmann, Lucian Shifren, Scott E. Thompson, Pushkar Ranade, Jing Wang, Paul E. Gregory, Sachin R. Sonkusale, Lance Scudder, Dalong Zhao, Teymur Bakhishev, Yujie Liu, Lingquan Wang, Weimin Zhang, Sameer Pradhan, Michael Duane, Sung Hwan Kim

33.  Electronic devices and systems, and methods for making and using the same

  • Patent number: 8975128
  • Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
  • Type: Grant
  • Filed: November 18, 2013
  • Date of Patent: March 10, 2015
  • Assignee: SuVolta, Inc.
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

34.  HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES

  • Publication number: 20150061012
  • Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
  • Type: Application
  • Filed: November 6, 2014
  • Publication date: March 5, 2015
  • Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane

35.  ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR

  • Publication number: 20150015334
  • Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
  • Type: Application
  • Filed: September 29, 2014
  • Publication date: January 15, 2015
  • Inventors: Lawrence T. Clark, Scott E. Thompson

36.  Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer

  • Patent number: 8916937
  • Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.
  • Type: Grant
  • Filed: February 14, 2014
  • Date of Patent: December 23, 2014
  • Assignee: SuVOLTA, Inc.
  • Inventors: Thomas Hoffmann, Pushkar Ranade, Lucian Shifren, Scott E. Thompson

37.  Transistor having reduced junction leakage and methods of forming thereof

  • Patent number: 8883600
  • Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
  • Type: Grant
  • Filed: December 21, 2012
  • Date of Patent: November 11, 2014
  • Assignee: SuVolta, Inc.
  • Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane

38.  Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom

  • Patent number: 8877619
  • Abstract: Structures and processes are provided that can be used for effectively integrating different transistor designs across a process platform. In particular, a bifurcated process is provided in which dopants and other processes for forming some transistor types may be performed prior to STI or other device isolation processes, and other devices may be formed thereafter. Thus, doping and other steps and their sequence with respect to the STI process can be selected to be STI-first or STI-last, depending on the device type to be manufactured, the range of device types that are manufactured on the same wafer or die, or the range of device types that are planned to be manufactured using the same or similar mask sets.
  • Type: Grant
  • Filed: January 23, 2013
  • Date of Patent: November 4, 2014
  • Assignee: SuVolta, Inc.
  • Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Lance Scudder, Dalong Zhao, Teymur Bakhisher, Sameer Pradhan

39.  Analog circuits having improved transistors, and methods therefor

  • Patent number: 8847684
  • Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
  • Type: Grant
  • Filed: February 19, 2013
  • Date of Patent: September 30, 2014
  • Assignee: SuVolta, Inc.
  • Inventors: Lawrence T. Clark, Scott E. Thompson

40.  TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATION THEREOF

  • Publication number: 20140284722
  • Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD, so that the body bias can be tuned separately from VT for a given device.
  • Type: Application
  • Filed: June 5, 2014
  • Publication date: September 25, 2014
  • Inventors: Reza Arghavani, Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve

41.  ANALOG TRANSISTOR

  • Publication number: 20140248753
  • Abstract: An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants.
  • Type: Application
  • Filed: May 9, 2014
  • Publication date: September 4, 2014
  • Applicant: SuVolta, Inc.
  • Inventors: Lucian Shifren, Scott E. Thompson, Paul E. Gregory

42.  Integrated circuit devices and methods

  • Patent number: 8811068
  • Abstract: An integrated circuit can include SRAM cells, with pull-up transistors, pull-down transistors, and pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer. The screening region has a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer. The screening region can provide an enhanced body coefficient for the pull-up transistors to increase a read static noise margin of the SRAM cell when a bias voltage is applied to the screening region. Related methods are also disclosed.
  • Type: Grant
  • Filed: May 14, 2012
  • Date of Patent: August 19, 2014
  • Assignee: Suvolta, Inc.
  • Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Robert Rogenmoser, Damodar R. Thummalapally

43.  Porting a circuit design from a first semiconductor process to a second semiconductor process

  • Patent number: 8806395
  • Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated.
  • Type: Grant
  • Filed: February 3, 2014
  • Date of Patent: August 12, 2014
  • Assignee: SuVolta, Inc.
  • Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Samuel Leshner

44.   Monitoring and measurement of thin film layers

  • Patent number: 8796048
  • Abstract: The present disclosure provides methods and structures for measurement, control, and monitoring the thickness of thin film layers formed as part of a semiconductor manufacturing process. The methods and structures presented provide the capability to measure and monitor the thickness of the thin film using trench line structures. In certain embodiments, the thin film thickness measurement system can be integrated with thin film growth and control software, providing automated process control (APC) or statistical process control (SPC) capability by measuring and monitoring the thin film thickness during manufacturing. Methods for measuring the thickness of thin films can be important to the fabrication of integrated circuits because the thickness and uniformity of the thin film can determine electrical characteristics of the transistors being fabricated.
  • Type: Grant
  • Filed: May 11, 2012
  • Date of Patent: August 5, 2014
  • Assignee: Suvolta, Inc.
  • Inventors: Scott E. Thompson, Pushkar Ranade, Lance Scudder, Charles Stager

45.  Transistor with threshold voltage set notch and method of fabrication thereof

  • Patent number: 8759872
  • Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD, so that the body bias can be tuned separately from VT for a given device.
  • Type: Grant
  • Filed: December 17, 2010
  • Date of Patent: June 24, 2014
  • Assignee: SuVolta, Inc.
  • Inventors: Reza Arghavani, Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve

46.  ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION

  • Publication number: 20140167156
  • Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
  • Type: Application
  • Filed: February 24, 2014
  • Publication date: June 19, 2014
  • Applicant: SuVolta, lnc.
  • Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson

47.  Process for manufacturing an improved analog transistor

  • Patent number: 8748270
  • Abstract: An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants. The channel is supported on a screen layer doped to have an average dopant density at least five times as great as the average dopant density of the substantially undoped channel which, in turn, is supported by a doped well having an average dopant density at least twice the average dopant density of the substantially undoped channel.
  • Type: Grant
  • Filed: July 20, 2012
  • Date of Patent: June 10, 2014
  • Assignee: SuVolta, Inc.
  • Inventors: Lucian Shifren, Scott E. Thompson, Paul E. Gregory

48.  CMOS gate stack structures and processes

  • Patent number: 8735987
  • Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
  • Type: Grant
  • Filed: June 6, 2012
  • Date of Patent: May 27, 2014
  • Assignee: Suvolta, Inc.
  • Inventors: Thomas Hoffmann, Scott E. Thompson, Pushkar Ranade

49.  DEPLETED MOS TRANSISTORS HAVING A SCREENING LAYER AND METHODS THEREOF

  • Publication number: 20140084385
  • Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.
  • Type: Application
  • Filed: September 5, 2013
  • Publication date: March 27, 2014
  • Applicant: SuVolta, Inc.
  • Inventors: Thomas Hoffmann, Lucian Shifren, Scott E. Thompson, Pushkar Ranade, Jing Wang, Paul E. Gregory, Sachin R. Sonkusale, Lance Scudder, Dalong Zhao, Teymur Bakhishev, Yujie Liu, Lingquan Wang, Weimin Zhang, Sameer Pradhan, Michael Duane, Sung Hwan Kim

50.  ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME

  • Publication number: 20140077312
  • Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
  • Type: Application
  • Filed: November 18, 2013
  • Publication date: March 20, 2014
  • Applicant: SuVolta, Inc.
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

51.  Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer

  • Patent number: 8653604
  • Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.
  • Type: Grant
  • Filed: September 21, 2012
  • Date of Patent: February 18, 2014
  • Assignee: SuVolta, Inc.
  • Inventors: Thomas Hoffmann, Pushkar Ranade, Lucian Shifren, Scott E. Thompson

52.  Porting a circuit design from a first semiconductor process to a second semiconductor process

  • Patent number: 8645878
  • Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated.
  • Type: Grant
  • Filed: August 22, 2012
  • Date of Patent: February 4, 2014
  • Assignee: SuVolta, Inc.
  • Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Samuel Leshner

53.  Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer

  • Patent number: 8629016
  • Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.
  • Type: Grant
  • Filed: April 30, 2012
  • Date of Patent: January 14, 2014
  • Assignee: SuVolta, Inc.
  • Inventors: Thomas Hoffmann, Pushkar Ranade, Lucian Shifren, Scott E. Thompson

54.  CMOS structures and processes based on selective thinning

  • Patent number: 8614128
  • Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.
  • Type: Grant
  • Filed: August 22, 2012
  • Date of Patent: December 24, 2013
  • Assignee: Suvolta, Inc.
  • Inventors: Scott E. Thompson, Thomas Hoffmann, Lance Scudder, U. C. Sridharan, Dalong Zhao, Pushkar Ranade, Michael Duane, Paul E. Gregory

55.  LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICATION THEREOF

  • Publication number: 20130328129
  • Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
  • Type: Application
  • Filed: August 19, 2013
  • Publication date: December 12, 2013
  • Applicant: SuVolta, Inc.
  • Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang

56.  Electronic devices and systems, and methods for making and using the same

  • Patent number: 8604527
  • Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
  • Type: Grant
  • Filed: September 14, 2012
  • Date of Patent: December 10, 2013
  • Assignee: SuVolta, Inc.
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

57.  Electronic devices and systems, and methods for making and using the same

  • Patent number: 8604530
  • Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
  • Type: Grant
  • Filed: September 14, 2012
  • Date of Patent: December 10, 2013
  • Assignee: SuVolta, Inc.
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

58.  Electronic devices and systems, and methods for making and using the same

  • Patent number: 8541824
  • Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
  • Type: Grant
  • Filed: July 19, 2012
  • Date of Patent: September 24, 2013
  • Assignee: SuVolta, Inc.
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

59.  Low power semiconductor transistor structure and method of fabrication thereof

  • Patent number: 8530286
  • Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
  • Type: Grant
  • Filed: December 17, 2010
  • Date of Patent: September 10, 2013
  • Assignee: SuVolta, Inc.
  • Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang

60.  ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION

  • Publication number: 20130181298
  • Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
  • Type: Application
  • Filed: March 6, 2013
  • Publication date: July 18, 2013
  • Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson

61.  ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR

  • Publication number: 20130154739
  • Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
  • Type: Application
  • Filed: February 19, 2013
  • Publication date: June 20, 2013
  • Inventors: Lawrence T. Clark, Scott E. Thompson

62.  Digital circuits having improved transistors, and methods therefor

  • Patent number: 8461875
  • Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
  • Type: Grant
  • Filed: February 18, 2011
  • Date of Patent: June 11, 2013
  • Assignee: SuVolta, Inc.
  • Inventors: Scott E. Thompson, Lawrence T. Clark

63.  Advanced transistors with punch through suppression

  • Patent number: 8421162
  • Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
  • Type: Grant
  • Filed: September 30, 2010
  • Date of Patent: April 16, 2013
  • Assignee: Suvolta, Inc.
  • Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson

64.  Analog circuits having improved transistors, and methods therefor

  • Patent number: 8400219
  • Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
  • Type: Grant
  • Filed: March 24, 2011
  • Date of Patent: March 19, 2013
  • Assignee: Suvolta, Inc.
  • Inventors: Lawrence T. Clark, Scott E. Thompson

65.  ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME

  • Publication number: 20130020639
  • Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
  • Type: Application
  • Filed: September 14, 2012
  • Publication date: January 24, 2013
  • Applicant: Suvolta, Inc
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

66.  ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME

  • Publication number: 20130020638
  • Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
  • Type: Application
  • Filed: September 14, 2012
  • Publication date: January 24, 2013
  • Applicant: SUVOLTA, INC.
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

67.  ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME

  • Publication number: 20120299111
  • Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
  • Type: Application
  • Filed: July 19, 2012
  • Publication date: November 29, 2012
  • Applicant: SUVOLTA, INC.
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

68.  ANALOG CIRCUITS HAVING IMPROVED TRANSISTORS, AND METHODS THEREFOR

  • Publication number: 20120242409
  • Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
  • Type: Application
  • Filed: March 24, 2011
  • Publication date: September 27, 2012
  • Inventors: Lawrence T. Clark, Scott E. Thompson

69.  Electronic devices and systems, and methods for making and using the same

  • Patent number: 8273617
  • Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.
  • Type: Grant
  • Filed: February 18, 2010
  • Date of Patent: September 25, 2012
  • Assignee: SuVolta, Inc.
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

70.  TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATION THEREOF

  • Publication number: 20110309447
  • Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD, so that the body bias can be tuned separately from VT for a given device.
  • Type: Application
  • Filed: December 17, 2010
  • Publication date: December 22, 2011
  • Inventors: Reza Arghavani, Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve

71.  LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICATION THEREOF

  • Publication number: 20110248352
  • Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
  • Type: Application
  • Filed: December 17, 2010
  • Publication date: October 13, 2011
  • Inventors: Lucian Shifren, Pushkar Ranade, Scott E. Thompson, Sachin R. Sonkusale, Weimin Zhang

72.  Electronic Devices and Systems, and Methods for Making and Using the Same

  • Publication number: 20110074498
  • Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.
  • Type: Application
  • Filed: February 18, 2010
  • Publication date: March 31, 2011
  • Applicant: SuVolta, Inc.
  • Inventors: Scott E. Thompson, Damodar R. Thummalapally

73.  Methods and articles incorporating local stress for performance improvement of strained semiconductor devices

  • Patent number: 7723720
  • Abstract: A packaged semiconductor device (450) includes a semiconductor chip (400) having at least one selectively thinned substrate (cavity) region (410). A package (460) is provided for mounting, enclosing and electrically connecting the chip (400) to the outside world, and structure for applying external stress (470) to induce strain in the thinned substrate region (410). The external stress is preferably adjustable, such as by varying the gas flow (or a vacuum) applied through a pressure valve.
  • Type: Grant
  • Filed: November 9, 2005
  • Date of Patent: May 25, 2010
  • Assignee: University of Florida Research Foundation, Inc.
  • Inventors: Toshikazu Nishida, Scott E. Thompson, Al Ogden, Kehuey Wu

74.  Methods And Articles Incorporating Local Stress For Performance Improvement Of Strained Semiconductor Devices

  • Publication number: 20090072371
  • Abstract: A packaged semiconductor device (450) includes a semiconductor chip (400) having at least one selectively thinned substrate (cavity) region (410). A package (460) is provided for mounting, enclosing and electrically connecting the chip (400) to the outside world, and structure for applying external stress (470) to induce strain in the thinned substrate region (410). The external stress is preferably adjustable, such as by varying the gas flow (or a vacuum) applied through a pressure valve.
  • Type: Application
  • Filed: November 9, 2005
  • Publication date: March 19, 2009
  • Applicant: University of Florida Research Foundation, Inc.
  • Inventors: Toshikazu Nishida, Scott E. Thompson, Al Ogden, Wu Kehuey

75.  Channel dopant implantation with automatic compensation for variations in critical dimension

  • Patent number: 6020244
  • Abstract: An improved well boosting implant which provides better characteristics than traditional halo implants particularly for short channel devices (e.g., 0.25 microns or less). In effect, an implant is distributed across the entire channel with higher concentrations occurring in the center of the channel of the devices having gate lengths less than the critical dimension. This is done by using very large tilt angles (e.g., 30-50.degree.) with a relatively light dopant species and by using a relatively high energy when compared to the traditional halo implants.
  • Type: Grant
  • Filed: December 30, 1996
  • Date of Patent: February 1, 2000
  • Assignee: Intel Corporation
  • Inventors: Scott E. Thompson, Paul A. Packan, Tahir Ghani, Mark Stettler, Shahriar S. Ahmed, Mark T. Bohr

76.  Process for forming doped regions from solid phase diffusion source

  • Patent number: 5877072
  • Abstract: A process for doping a region in a substrate from a solid phase source. An inert gas is bubbled through a dopant containing ester and supplied to a chamber along with the gases used to form a silicon dioxide layer such as a TEOS formed layer. The flow of the inert gas can be modulated to grade the dopant concentration in the silicon dioxide layer. The dopant is diffused from the silicon dioxide layer into the substrate to form, for instance, source and drain regions in field-effect transistors.
  • Type: Grant
  • Filed: March 31, 1997
  • Date of Patent: March 2, 1999
  • Assignee: Intel Corporation
  • Inventors: Ebrahim Andideh, Scott E. Thompson

77.  Two step source/drain anneal to prevent dopant evaporation

  • Patent number: 5874344
  • Abstract: A two step source/drain annealing process which permits a dopant to be ion implanted directly into the silicon without a protective oxide. The gate oxide is removed before the ion implantation of the dopant occurs, thus the dopant is implanted directly into bare silicon. In a first step of the annealing process, a thin oxide is grown over the source and drain regions at a relatively low temperature (e.g., 600.degree. C.) this temperature to prevent the evaporation of the dopant from the silicon substrate and polysilicon gate. The second step of the annealing process occurs at a higher temperature allowing the dopant to be driven into the substrate forming the source and drain regions.
  • Type: Grant
  • Filed: December 30, 1996
  • Date of Patent: February 23, 1999
  • Assignee: Intel Corporation
  • Inventors: Scott E. Thompson, Chai-Hong Jan

 

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